1. Field of the Invention
The present invention relates to packet switches, and more particularly to an asynchronous transfer mode packet switch for use in a broadband integrated services digital network.
2. Description of the Prior Art
The broadband integrated services digital network (BISDN) has become increasingly popular in recent years as consumers' demand for high speed and high density data communications has accelerated. The BISDN offers high speed, high bandwidth capabilities while integrating voice, video, and data over a single network.
To make the fullest use of BISDN bandwidth and speed, optical fiber has been used extensively because optical fibers can carry large amounts of data at high speed. However, switching technology has not developed as rapidly as fiber technology and is currently not fast enough to take full advantage of BISDN and optical transmission capacity.
To provide a basis for the development of new switching technology and to provide for uniformity in the data transmission industry, the CCITT has developed standards for switching in BISDNs. The CCITT standards recommend the implementation of asynchronous transfer mode packet switching in BISDN applications. Asynchronous transfer mode packet switching utilizes packet switches for routing information in fixed width data packets between a plurality of inputs and outputs. Each data packet typically includes 48 bytes of data and 5 bytes of header information. The header information is used by the packet switches to route the packets asynchronously between the input and output devices. A single asynchronous transfer mode network may carry hundreds of thousands of asynchronous transfer mode packets per second.
A number of asynchronous transfer mode packet switches have been developed for use in BISDNs. Prior art asynchronous transfer mode packet switches generally fall into two categories: single stage switches and multistage switches.
The knock-out switch is a well-known example of a single stage packet switch. The knock-out switch utilizes a crossbar or similar type architecture with each output port able to access all input lines simultaneously. By using a crossbar architecture, the knock-out switch has a simple, self-routing, non-blocking, low latency configuration with a high degree of modularity and expandability.
However, the knock-out switch architecture suffers from several limitations that limit its use in broadband applications. For example, an N.times.N knock-out switch that accepts a maximum number of L packets in a time slot requires N packet filters and an N.times.L concentrator for each output port. This large number of packet filters and large concentrator significantly increases the cost and complexity of the packet switches, especially for networks with a great number of inputs and outputs.
Another limitation of the knock-out switch architecture is that it utilizes a large number of memory buffers for output buffering and requires memory speed-up to accept multiple packets simultaneously at each output port. Additionally, knock-out type switches do not include means for sorting data packets for priority and therefore require additional hardware for this function. Finally, the implementation of multicasting in a knock-out switch requires each output port to first accept all multicast packets and then to reject those that do not belong to it. This also requires additional hardware including large memory buffers to store all the multicast addresses and additional logic to determine whether to accept or reject a multicast packet at the output port.
The starlight switch is a well-known example of a multi-stage packet switch. Multi-stage packet switches use banyan networks as concentrators and routers and employ input queuing, output queuing, internal queuing, or some combination of these queuing methods. The starlight switch architecture includes a batcher sorting network, a trap network, and a banyan router. The trap network allows only one packet to arrive at an output port and recycles the remainder through the sorter during the next time slot. The packets being recycled go through a delay line to align them with the next time slot. The starlight switch is efficient and inexpensive because it incorporates shared input buffering using simple delay lines to reduce the size of the buffer requirements. Additionally, the starlight switch implements simple priority protocols without increasing the buffer size and has a low switch latency.
However, the starlight switch also suffers from several limitations that limit its utility in broadband applications. For example, to achieve low packet loss, the starlight architecture requires a large sorter and trap network, thereby increasing the number of sorting and switching elements severalfold. Additionally, the starlight architecture is not modular or expandable in small increments and requires a separate copy network, thus increasing the cost of the switch.
Another type of prior art packet switch is known as a shared buffer switch. In this data packet switching approach, all the data packets received by the switch during one cycle are written into a memory within one clock cycle and then read from memory by the output ports one at a time. These switches are also limited because they must be operated at a much higher speed for writing all the packets in one clock cycle, thus often introducing head-of-line blocking. Additionally, these switches do not offer a priority mechanism and are not modular.
Many variations of the above three types of switches have been developed including hybrid combinations. However, none of the prior art asynchronous transfer mode switches is able to provide all the desired features while maintaining low complexity and low cost implementation.
Accordingly, there is a need for an improved asynchronous transfer mode packet switch that overcomes the limitations of the prior art.